This invention is generally related to processor and computer architectures, and more particularly to the processing of, including arbitration among, requests for accessing a storage area such as a processor cache or a register file.
High performance storage areas such as a processor cache or a register file help improve the overall performance of a computer system, by providing high speed access to frequently used data. Once the area has been accessed, the stored data can be delivered to the requestor at very high speeds (relative to, for instance, deliveries from main memory or a hard disk). However, the ability of a cache or register file to accept a large number of access requests in the same clock cycle (the so-called xe2x80x98bandwidthxe2x80x99 here) is very limited. The performance of such storage areas are being pushed to their limits by increasingly complex processor and computer architectures in which a large number of requesters can seek access to the same storage area. For instance, in some high performance architectures, a processor cache which can accept at most only one access request every other clock cycle might be saturated by two or more of the following requesters seeking access to the cache in the same clock cycle: a high speed execution core which generates one request, on average, in each clock, and an instruction fetch unit, a page miss handler, and a bus interface, each of which can generate one request every few clocks. Once the cache is saturated, subsequent requests to the cache are rejected. If the cache stays saturated for a long period of time, there is a risk that certain requestors will continue to be repeatedly rejected and thus be xe2x80x98starvedxe2x80x99, thereby rendering a performance degradation or, in the worst case, a malfunctioning computer system. Efforts to increase the access bandwidth of the cache may be hampered by the significant increase in cost associated with such a change.